As the builder of AMOS, the BlueGene/Q supercomputer that sits at the heart of the Center for Computational Innovation, IBM is well-aware of the power that scientific computing and simulation brings to the research table.
RPI has been able to employ its own expertise in modeling and simulation to address a wide array of the engineering issues that crop up routinely at the forefront of semiconductor manufacturing research. The insights that come out of this the RPI/IBM collaboration are put to use in IBM’s research and manufacturing facilities on an ongoing basis. Some of the questions that have been looked at impact manufacturing at several different scales: leading edge lithography, alignment issues in memory and logic devices, and reliability in packaging.
PROCESSING SCALE: Extreme Ultraviolet Lithography
Extreme ultraviolet lithography (also known as EUV) is a next-generation lithography technology using the high energy wavelengths that can carry the industry down to the 7 nm technology node and beyond. But with the cost of EUV masks exceeding those of traditional lithographic masks by wide margins and with the much smaller pattern details represented by the new masks, protecting their physical integrity is essential.
Proposed films, called pellicles, that can sit over the valuable masks are challenging to engineer, but represent an important part of the EUV lithography trajectory.
Working closely with IBM technologists, RPI has been able to simulate proposed pellicles only a few tens of nanometers thick as they absorb high doses of extreme ultraviolet radiation in tiny exposure windows and heat up to thousands of degrees while being subjected to several Gs of acceleration. Being able to predict a priori the thermomechanical response of these important protective films is driving new innovations for stabilizing them, before they are used in equipment costing tens of millions of dollars.
DEVICE SCALE: Deep Trench Shifts
Semiconductor processes are almost legendary for their multi-material, multi-physics, multi-step nature. But this combination of widely varying materials and properties creates challenges for compatibility.
Such a mismatch drove a recent investigation into the thermo-mechanical behavior of a common structure in memory and logic circuits: the deep trench capacitor. Formed in arrays of thousands by depositing a sandwich of conductors and dielectrics into series of high-aspect ratio holes in the surface of silicon wafers, DTs, as they are known, can be pushed into stress states by aggressive combinations of materials processing and size scaling. With enough internal stress they can distort the very materials they are made from, and in extreme cases, the silicon wafers themselves can experience observable bending!
Employing highly advanced codes developed in conjunction with Sandia National Laboratory, RPI ran massively parallel simulations to isolate the mechanical response of large arrays of DTs when highly stressed dielectrics were deposited. Even when the shifts of individual DT structures were small, the accumulation of the distortion over large arrays can result in end-to-end misalignments that severely impact highly tuned manufacturing processes. With the success of the DT project, RPI and IBM have launched a second phase, in which FinFET and other advanced gate stacks are to be analyzed for their mechanical response to materials with built-in stress states.
PACKAGE SCALE: Solder Joint Arrays
The highly compact size of an integrated circuit is one of its advantages, but when it comes to making connections to the IC from the outside world or dissipating the heat it generates, those diminutive proportions work against it.
That is why every microelectronic die that comes off a production line needs to be embedded in a highly engineered package. The distinctive look of these packages, with their pins and electrical leads, has become synonymous with our image of microchips. Because the packaging process takes place at the end of the production pipeline, it involves the chip when it is already in its most valuable form; any mistake made here can ruin hundreds of hours of expensive production process!
Packages are typically connected to IC dies by large arrays of tiny balls of solder, each only a few tens of micrometers in diameter. Thousands of these solder balls are sandwiched between contacts on a package and a die and then heated until they just begin to melt and wick onto the contact pads, forming excellent electrical and thermal connections. However, during the resulting cool down period, the differential contraction of the package and the die can put these miniscule solder joints under substantial stresses, leading to physical damage to the highly valuable die. RPI has designed a simulation methodology that allows various cool down trajectories to be investigated easily and without tying up expensive processing equipment.
To perform these simulations, RPI had to create novel material models that account for high temperature creep during processes already subject to plastic deformation, and implement those models in the same highly advanced parallel code developed in conjunction with Sandia and used for the DT shift project. Employing 16k+ processors on AMOS, we were able to solve those models on meshes with billions of elements, looking at arrays of up to 4,096 solder balls. In the next phase of this project, RPI is working with IBM to incorporate the behavior of crystal dislocations in the conductors, both in packaging and other applications.